1. Field of the Invention
The present invention relates to the testing of integrated circuits and, more specifically, to the functional testing of integrated circuit chips by means of two physical contact points, generally by devices of tip board type. The present invention more specifically relates to the testing of contactless transponder integrated circuits intended for so-called secure applications where circuits internal to the chip operate asynchronously with respect to its outer environment.
2. Discussion of the Related Art
FIG. 1 shows, in a simplified view and in the form of blocks, an example of a conventional test of an integrated circuit 1. Such a tester comprises a contacting element 2 provided with two points 3, 4 of connection to pads corresponding to the integrated circuit chip. Chip 1 rests upon a support 5 of the tester and tip board 2 communicates with a central unit (UC) 6 of the test system.
FIG. 2 very schematically shows in the form of blocks a chip 1 of the type to which the present invention applies. Chip 1 comprises an area 2 comprising the processing circuits linked to the application and two input/output pads 11, 12 of this area. Pads 11 and 12 are more specifically intended to be subsequently connected to the ends of an inductive winding taking part in a resonant circuit, generally parallel, in an application to an electromagnetic transponder. The functional test to which the present invention relates includes of testing the circuit before assembly with its resonant circuit.
The functional testing, also called radiofrequency mode testing, is generally performed by using pads 11 and 12 for points 3 and 4 of the tester.
In so-called non-secure applications, a functional testing is generally carried out by connecting several integrated circuits in parallel. Such a testing is thus carried out by integrated circuit wafer, before cutting.
In so-called secure applications, a specific problem is that the operation of integrated circuit chips is voluntarily desynchronized to prevent piracies based on a synchronized operation, based on a clock external to the chip, of secret quantities or secret algorithms contained by the chips. The chips thus all respond with variable non-predictable delays to control signals received on their respective pads 11 and 12. Such a characteristic of secure products prevents parallel tests of several chips, which considerably increases the duration of testing.